Novel Hamming code for error correction and detection of higher data bits using VHDL

Hamming code is familier for its single-bit error detection & correction capability. To provide such a capability, it introduces 4 redundancy bits in a 7-bit data item. These redundancy bits are to be interspersed at bit positions (n = 0, 1, 2, 3) with the original data bits. After error detection & correction, if any, the data bits have to be reassembled by removing the redundancy bits. In the proposed improvement, the redundancy bits will be appended at the end of data bits. This eliminates the overhead of interspersing the redundancy bits at the sender end and their removal at the receiver end after checking for single-bit error and consequent correction, if any. Further the effort needed in identifying the values of the redundancy bits is lower in the proposed novel method. Hamming code is normally used for transmission of 7-bit data item. Scaling it for larger data lengths results in a lot of overhead due to interspersing the redundancy bits and their subsequent removal. In contrast, the proposed method is highly scalable without such overhead. Hence, this feature is suitable for transmission of large size data bit-streams with much lower redundancy bits per data bit ratio. In this paper we have proposed an efficient and novel Hamming Code algorithm, for finding error location and correction to optimize the load on receiver end and reduce delay in the circuit. Simulation is done using Xilinx 9.2